PowerPC Linux Box
The PPC604e, PPC740 and PPC750 are very powerful RISC processors, exceeding
the performance of Pentium, Pentium II and Pentium III.
The PPC604e, PPC740 and PPC750 all share a common bus standard (known as
the 60x-bus), also to be used by the next generation PowerPC CPU's (G4).
This bus and the processors mentioned are all fully multiprocessor capable,
making the comparision with the Pentiums even more favorable, as only the
very high cost Pentium Xeon's support more than two-way SMP.
Apple, IBM and Motorola originally defined two different hardware platforms
for desktop computers based on the PowerPC: the PowerPC Reference Platform
(PReP) and the Common Hardware Reference Platform (CHRP). Today CHRP is
recognised as the standard.
Linux 2.x runs unmodified on a CHRP-compliant PowerPC system and supports
Symmetrical Multi Processing (SMP) as defined in the CHRP standard. Today
most PowerPC Linux-systems are running on PowerMac's (whether they are
CHRP-compliant or not, is not clear, but they are anyway subject to Apples
The CHRP Specification
The CHRP specification details the capabilities in terms of hardware and
software interfaces that must be present on a system that is to be called
CHRP-compliant. The specification has many optional enhancements (power
management, SMP, ...), but the basic requirements are quite small, yet
powerful enough to let a full-blown OS like Linux run on it.
Note specifically that no need for display, keyboard, mouse or specific
hard disk interface (IDE, SCSI) is required. Some kind of boot device is
of course needed, but this could in principle be a solid state disk (Flash).
Support for many of the devices known from the PC world is encouraged (PS/2
keyboard & mouse, VGA graphics card, Ultra DMA/33 IDE Controllers and
much more), and is directly supported by Linux when present (and
implemented according to the CHRP specification, of course).
The main CPU must be a PowerPC that supports the Virtual Operating Environment
specified in the PowerPC architecture. In practice this boils down to,
that the CPU must be a desktop PowerPC (like the 603, 604, 740, 750, G4,
...) with support for demand-paged virtual memory and protection, and not
an embedded PowerPC (like the IBM 400-series or the Motorola 500- or 800-series).
8 MB or more random access memory for the OS.
At least one PCI bus must be present in the system.
An OpenPIC compatible interrupt controller must be present in the system.
The specification for an OpenPIC interrupt controller has been put together
by various independent industry forces, including AMD and Cyrix. The result
is a very elegant and expandable interrupt controller with full SMP support
(interrupt distribution etc.).
The presence of an ISA bus is optional, but if present, basically the periferals
from the legacy PC must be present: 8237-like DMA and dual 8259 PIC (in
addition to OpenPIC).
At least 8 KB Non-Volatile storage (NVRAM), a Real Time Clock (RTC) and
The boot code, typically residing in a flash, must present a client interface
to the OS compatible with that of the IEEE Standard for Boot (IEEE P1275-1994),
also known as Open Firmware (OF). The purpose of the OF is to do the low-level
boot initialisation, load and launch of the OS in a standard way. The OF
provides access to a number of data structures in the NVRAM that describes
the characteristics of the particular platform, and that can be used to
e.g. control the boot process (which OS to load etc.). Furthermore, the
boot code must provide an interface to Run Time Abstraction Services (RTAS)
used by the OS. The purpose of the RTAS is to abstract the actual implementation
of some of the hardware devices, such as: access to the PCI controller
to make memory mapping and configuration cycles, access to the NVRAM, access
to the RTAS, access to power management services, aiding the OS in low-level
fault diagnostics. By using this principle, the OS no longer needs to know
the individual chip sets in a system, as is the case in the PC world, and
similarly the chip set implementation is not constrained by the need to
be backwards register compatible with older versions.
Motorola has made a so-called Yellowknife X4 ATX-sized reference design
that incorporates a socket for a PowerPC CPU (604/740/750), SDRAM, boot
Flash, PCI Bridge (MPC106), PCI sockets, ISA bus & sockets. This board
is available to developers only at an uncompetitive price for evaulation
of the PowerPC processors and the architecture. Furthermore, this board
is not even CHRP-compliant, as it does not implement the OpenPIC interrupt
controller. But significant inspiration can be gained from the design.
The highest performance PowerPC CPU is currently the PPC750. It ships in
a 360-pin PBGA requiring 5W@1.9V at 466 MHz, featuring 64KB 8-way associative
L1 cache, runs with up to 1MB, 2-way associative L2 cache at 233 MHz (on
a decicated 64-bit backside bus, using standard syncronous static sync-burst
RAM's) and is completely LVTTL (3.3V) compatible at the I/Os. It fully
supports SMP (MESI cache architecture).
Motorola has a single chip "North Bridge", 304 pin PBGA MPC106, that performs
a glueless interface between 1-4 PowerPC CPU's, 1-8 64-bit wide SDRAM banks
(of up to 256 MB each), an 8-bit boot device (Flash) and a PCI bus. IBM
has a similar chip, the name of which I don't recall.
Winbond and other vendors make single chips (160-208 pins PQFP) for bridging
between the PCI and ISA buses, and implementing IDE interfaces.
National Semiconductor and other vendors make single chips (Super I/O's)
that implement all the standard ISA peripherals: 8254, 2x8259, 2x8237,
PS/2 Keyboard Interface, PC/2 Mouse Interface, EPP Parallel Port, 2xHigh
Speed Serial Port, RTC, NVRAM as well as interfaces for external ISA slots.
As should be apparent from the above, it is possible to build a powerful
PowerPC system based on the minimal subset of the CHRP specification, using
basically only the CPU, the North Bridge, a Flash device and a SDRAM array.
By adding some more components, full legacy ISA support can be added at
the cost of more design time, more real estate (big PQFP's, buffers and
connectors) and more complicated PCB layout and production (but the Yellowknife
X4-design is said to be only a 4-layer board!)
A lot of hardware design details must be cleared:
On the software front we have:
Should PowerPC CPU's be placed on daughter boards using some kind of socket
(e.g. 2 sockets with 1 or 2 CPU's in each socket)? This would make the
main board independent of the choice of CPU, prepared for the G4's, enable
easy scalability, allowing for 4-way SMP in a very limited board space.
On one hand the design would be simplfies through a divide-and-conquer
principle, but on the other hand the electrical design might get more difficult.
What sockets can be used (168-pin sockets for SDRAM?).
Design of the 100 MHz CPU bus and the 100 MHz SDRAM interface (especially
difficult if multiple CPU are present on daughter boards)
Design of the 233 MHz L2 cache-interface if the PPC750 is used
How to implement OpenPIC (find a suitable chip or make it in cheap FPGA?)
Clock distribution (MPC950)
PowerPC core power supply design (1.9V 7A/CPU)
Power management (both cooling and low-power-modes)
NVRAM and RTC details
ATX mechanic details (if applicable)
North Bridge details - what to use
PCI-ISA bridge details - what to use (if applicable)
ISA peripheral details - what to use (if applicable)
Are we sure that the trees grow into the sky, and that Linux supports CHRP
systems (even SMP) this well? What does it expect from OF/RTAS and the
hardware. Examine the source code.
How complex is the OF? Can we write it our selves or do we need to license
it from e.g. OpenFirmware (http://www.openfirmware.com)? Evaluate the IEEE
To my knowledge, no CHRP platform is easily commercially available for
end users. In the PowerPC world it seems that the focus is either on the
Apple PowerMAC desktops or the embedded market. The apperance of a powerful
operating system like Linux can change this! Because of the portability
of Linux and the applications running on it, the foundation for a desktop
system not based on the Windows/i386 or the Apple OS/PPC is suddenly possible.
With an easily scalable system, that has SMP-support built-in, a whole
range of products/projects emerge, ranging from complete multiprocessor
ATX-sized motherboards with PCI and ISA buses and peripherals for end-user
desktops to small match-box sized embedded boxes, all running Linux.
Bear in mind that all this could also in principle be done on an Alpha-processor
based system. The Alpha is indeed a powerful processor architecture, maybe
even more powerful than the PowerPC, but seen from the view of a kitchen-table
project, the PowerPC world seems much more within reach in terms of support
and availability of the necessary components and circuitry.
If you don't believe that you can change the world, what are you
doing here anyway?
Various PowerPC Datasheets: MPC750, MPC106 - I have it in PDF
CHRP Specification - I have it in PS/PDF
OpenPIC Specification - I have it in PDF
IEEE P1275-1994 - I have it in PDF
Winbond PCI-ISA bridge - I have it in PDF
National Semiconductor Super I/O - I have selection guide in HTML
Motorola Clock Distribution - I have selection guide in HTML
Various SDRAM, SSRAM and Flash Datasheets - I have it in PDF
Yellowknife Documentation - I have it in PDF
ATX Motherboard Specification - I have it on print
Linux 2.x kernel source code - freely available on the internet